There are applications (most often in the test and measurement industry), where a periodic signal passes through a medium with an additive noise, with the noise level exceeding (and sometimes far exceeding) the signal level. In many situations, it is desired to process a noisy periodic signal to eliminate, or substantially suppress, the noise component, to obtain a replica of the original periodic signal. An effective method of noise suppression and production of a replica of the original signal (with reduced noise) is based on an accumulation of samples of a number of signal periods with simultaneous or subsequent averaging.
A block diagram of an exemplary conventional apparatus 10 for periodic signal reproduction is shown in FIG. 1. As shown in that figure, apparatus 10 includes an analog signal input 10A for receiving an analog signal to be processed, a sampling input 10B for receiving a sampling clock signal, and an output terminal 10C for providing a system output signal.
Apparatus 10 further includes (i) an analog to digital converter (ADC) 11 having an analog signal input 11A coupled to input 10A for receiving an applied analog signal to be processed, an ADC sampling clock input 11B coupled to input 10B for receiving an applied ADC sampling clock signal and an ADC output 11C, (ii) an adder 12 having a first input 12A coupled to ADC output 11C, a second input 12B and an adder output 12C, (iii) a memory 14 having a WRITE input 14A coupled to adder output 12C, a READ output 14B coupled to system output 10C and an address input 14C, and (iv) a Modulo N counter 16 having a count input 16A coupled to input 10B for receiving the sampling clock signal and a count output 16B coupled to address input 14C.
In operation, ADC 11 receives a periodic (at frequency FS) analog signal to be processed at its input 11A, and an ADC sampling clock (at frequency FC) at its input 11B. In response to the analog signal and the sampling clock, ADC 11 provides a digital signal in the form of a succession of digitized samples of the analog signal, at ADC output 11C. That succession of samples summed with a succession of previously stored sample values by way of memory output 14C of memory 14 and adder input 12B, is applied via adder 12 to the WRITE input 14A of memory 14.
The frequency of the ADC sampling clock Fc is chosen with respect to frequency FS, in such a way that a period of the periodic analog signal to be processed contains an integer number N samples per period of the analog signal produced by the ADC 11. Thus, the ADC sampling frequency Fc is a harmonic of the signal frequency FS: Fc=N·Fs.
The input 16A of the modulo N counter 16 receives the sampling clock from sampling clock input 10B, so that the counter 16 in effect counts the number of samples at the output 11C of ADC 11 (the counting being done by modulo N). The number at the counter output 16B indicates the number of a “current” sample position in the period of the analog signal applied from analog signal input 10A. The output 16B of counter 16 is applied to the address input 14C of memory 14. In response to each successive count value, the current sample value at the adder output 12C is entered in a location, or cell, of memory 14 having an address that corresponds to the position of the sample in the then-current period of the analog signal. As a result, the next sample produced by ADC 11 is added by adder 12 to the number, or value, at the READ output of memory 14, and the resultant sum is written into a corresponding cell of memory 14.
After the applied periodic analog signal has been so-processed for M periods of the analog signal, that memory cell contains a sum of M samples, where M is the number of appearances of the corresponding position during the signal acquisition. Each sample at the ADC output 11C is representative of a sum of a “true” value of an underlying base (without noise) component of the analog signal applied at input 10A, and a value representative of a noise component of the signal applied at input 10A. As a result, a sample at the memory output 14C (and system output 10C) at each time instant, corresponds to a specific period position (in the applied analog signal), and equals the sample true value multiplied by M plus the sum of noise values which have appeared in this position of the period. If the number M is sufficiently large, the noise contribution in the output sample becomes negligibly small as opposed to the contribution the “true” values, and the signal at the memory output 14C for all practical purposes repeats the period of the applied periodic analog signal but without the noise components. This prior art method of periodic signal detection based on accumulation and averaging is in part effective, but is characterized by substantial limitations, particularly when the frequency of processed signal is high, as described below.
The relative efficiency of detection of periodic signals based on accumulation and averaging, caused its widespread application in a great variety of devices and systems (see, for example, U.S. Pat. No. 6,909,979; No. 7,362,795; No. 7,382,304; No. 7,813,297; US Patent Application Publication US2015/0204649; and others). However, the use of accumulation and averaging, when the frequency of processed signal is high, has met with substantial difficulties. Processing signals with high frequency requires use of high speed ADCs, which are typically built as composite units consisting of a number of time interleaved sub-ADCs with a common input and sequential timing. In general, for such time interleaved ADCs, the DC offsets as well as amplitude and phase frequency responses of the different sub-ADCs are not identical, resulting in specific signal distortions, for example, including the appearance of spurious frequency components. Such signal distortions are significantly detrimental to the performance of periodic analog signal averaging using composite ADCs based on time interleaved sub-ADC configurations.
The correction of distortions of composite ADCs caused by DC offsets mismatch of sub-ADCs, may be accomplished using compensation based on average values of DC offsets of the respective sub-ADCs (see U.S. Pat. No. 9,172,388), while the misalignment of frequency response may be rectified by equalization (see U.S. Pat. No. 7,408,495, No. 8,284,606 and others). The direct use of these conventional methods in the case of periodic signals averaging, presents certain difficulties because of the difference in the required accumulation. In particular, to effect correction of mismatched DC offsets and misalignments of the frequency responses, the accumulation should be performed for each sample in an interval that equals the number of sub-ADCs in the composite ADC multiplied by the composite ADC period, while the averaging of the periodic signal requires an accumulation for each sample in an interval that equals the number of ADC sample periods in the processed signal period. Thus, determination of the respective corrections by prior art methods for use with composite ADC-based configurations, is subject to conflicting requirements.
The subject technology provides an improved method and apparatus for periodic signal averaging that provides correction of the distortions typical for the composite ADCs.